1. Field of the Invention
The present invention relates generally to protection circuits and, more specifically, to circuitry which protects against electrostatic discharge (ESD) in an integrated circuit.
2. Discussion of the Prior Art
I. Electrostatic Discharge
Electrostatic discharge (ESD) in semiconductor integrated circuits (IC's) is a well-known problem. The inadvertent presence of a sudden voltage spike in an integrated circuit can cause physical destruction of circuit features For example, ESD-induced spikes can rupture the thin oxide gate of field effect transistors (FET's), or degrade P-N junctions, effectively destroying proper IC operation. A typical silicon dioxide gate will rupture when its dielectric strength is more than approximately 10.sup.7 V/cm.
The most common source of ESD stress is user handling of IC packages. The human body can accumulate a static electric charge as high as 2000 V, or an amount of charge that can easily rupture the gate oxide or other IC features.
The most common method of guarding against ESD is to insert a diode in shunt to the line of interest to provide a resistive path to divert the ESD spike. See, e.g., U.S. Pat. No. 4,890,187 (Tailliet et al) and IBM Technical Disclosure Bulletin, Vol. 22, No. 10. Another solution is to connect a field effect transistor (FET) in shunt to the line of interest and operate it in a gate-controlled drain avalanche breakdown mode. See, e.g., U.S. Pat. No. 4,692,834 (Iwahashi et al). However, these methods have had limited success Typically, they have been used only to protect circuit inputs. Further, as feature size continues to be reduced in IC fabrication, the oxide barrier between the gate and channel of FET's used in the IC becomes ever thinner and breakdown becomes more likely.
II. Floating Gate Transistors
In a conventional FET, application of a sufficient voltage at the control gate causes the channel region to become conductive, and a current flows from source to drain. In a floating gate FET, the same is true, but the voltage required to induce the channel to conduct is substantially higher than in a conventional FET.
FIG. 1a shows the physical structure of a conventional floating gate FET (n-channel). The floating gate FET includes a floating gate 2 which is electrically isolated from control gate 4 by a dielectric region 3, such as layered silicon dioxide. Both gates are electrically isolated from the underlying channel region 9 of the FET by the dielectric region. The channel region 9 is defined by identical n.sup.+ -type source 6 and drain 8 regions formed in p-type substrate 7. Typically, the source 6 is connected to substrate 7 (usually grounded) and a positive potential is applied to the drain 8 via conductive metal layers connected to the source and drain regions through openings formed in the oxide layer 3. The equivalent circuit symbol is shown in FIG. 1b. It is to be understood, however, that source and drain regions are virtually interchangeable in a FET.
Floating gate transistors are popular for use in memory devices, such as erasable-programmable-read-only-memory (EPROM), due to their ability to retain a charge across the floating gate 2 for long periods of time regardless of whether ordinary circuit voltages are applied to the circuit. This is true because a relatively large voltage (compared to circuit voltages) is required to overcome the oxide barrier and store or release a charge on the floating gate. The charge state is achieved by driving the drain junction to avalanche breakdown, so that high energy electrons will penetrate the thick oxide and become trapped on the floating gate. The charge is erased by shining ultraviolet light onto the device, thereby exciting the trapped electrons and causing them to move off the floating gate.
The floating gate voltage V.sub.F which is required to store a charge on the floating gate can be expressed as
V.sub.F =V.sub.G *C.sub.2 /(C.sub.1 +C.sub.2)],
where
C.sub.1 =the effective capacitance between the floating gate and the channel;
C.sub.2 =the effective capacitance between the floating and control gate; and
V.sub.G =the voltage at the control gate. The floating gate voltage V.sub.F may be adjusted during fabrication of the device by using conventional diffusion or ion implantation techniques to adjust the dopant levels in the channel. Alternatively, the ratio of effective capacitances may be adjusted by varying the oxide thickness.
When a sufficient potential V.sub.G is applied at the control gate 4, current is induced to flow across channel 5 from source 6 to drain 8.
A floating gate transistor may thus be used in a novel way, without regard to the charge-injection model just described, to protect against ESD, as will be hereinafter discussed.